Make Variables

Make variables come from different sources
the command line
the makefile
environment variables

Make uses a number of predefined variables
CC, CFLAGS (compiler and arguments)
LD, LDFLAGS (linker and arguments)
@, *, <, ^ (target, stem, dep.)
MAKE (make and its own arguments)

Variables are only expanded when used
Unless you use ":=", but please don't overdo

This is a simple makefile
         CFLAGS = -O2 -g -Wall
         all: prog1 prog2