SPI in LPC11Uxx


Our microcontroller family has 2 SPI controllers
Then, MISO, MOSI and SCK can sometimes be routed to different pins
They work as either master or slave (most uC do the same)

The logic cell includes a FIFO (everyone does)
This allows some CPU relief
You can manage an uninterrupted data stream

You can also do bit-banging SPI
There are no specific GPIO requirements
Bit-banging is slow, and not usually a wise choice
A single SPI master can drive many peripherals, so we don't need more buses

I personally prefer driving SSEL from a GPIO pin
You can have as many CS as you need, independent of hw features
You can implement whatever policy for CS activation