SPI: Variations on the base idea

Currently, quad-spi (QSPI, QPI) flash memory is common
Same basics as SPI, but with 4 data lines
Usually, commands are on MOSI and data is by nibbles
The chip may support dual-SPI too
The hardware designer must trade between tracks and speed



Some devices provide
   for strange daisy-chain
   configurations
Tey act like one device,
            e.g. many ADC channels
Very handy, but not trivial
            to get right