Interrupts in ARM

The ARM architecture has a special approach to traps
The CPU jumps to a specific address (0..0x1c)
The CPU changes its interanl "mode"
Some registers are swapped to a different "bank"
The PC is set to the "vector" address (0x00..0x1c)

Thus, no automatic memory access is perfomed

        b       reset
        ldr     pc, _undefined_instruction
        ldr     pc, _software_interrupt
        ldr     pc, _prefetch_abort
        ldr     pc, _data_abort
        ldr     pc, _not_used
        ldr     pc, _irq
        ldr     pc, _fiq

This approach simplifies hardware but makes software not trivial
Not a problem, usually, when you code this once only