Interrupts in Cortex-M0 (LPC11)

The NVIC (Nested Interrupt Controller) is part of Cortex-M0
It is a peripheral device like times and I/O ports
But ARM includes it in the processor definition
The reset/interrupt mechanism is highly coupled with it
At address 0, we find the interrupt vectors
They are vectors (pointers), not instructions
The CPU pushes processor state to the stack
It then fetches the vector to the program counter
What happen is similar to a function call
16 Core vectors
0: initial stack pointer
1: reset vector
2..15: more predefined traps
32 (or 64) SoC-specific vectors
LPC1135 and similar ones use 32 vectors
They are internal timers and peripheral devices

See chapters 6 and 24.3 of the uC manual (it's committed)